In the existing sub-20 nm technology, a three-dimensional multi-gate device (FinFET or Tri-gate) becomes the main device structure, and such a structure enhances the gate control capability and suppresses the current leakage and short-channel effects.
For example, as compared with the traditional single-gate bulk Si or SOI MOSFET, a dual-gate structured MOSFET can suppress the Short Channel Effect (SCE) and the Drain Induction Barrier Lower (DIBL) effect, has lower junction capacitance, can realize light channel doping, can adjust a threshold voltage by setting the work function of the metal gate to obtain about twice the drive current, thus reduces the requirement on Equivalent Oxide Thickness (EOT). However, a tri-gate device has a much stronger gate control capability as compared with a dual-gate device since the gate encloses the top surface and the two sides of the channel region. Further, an all-around nanowire multi-gate device has more advantageous.
Generally, nanowire three-dimensional multi-gate devices shall be integrated with the metal gate last process to keep the performance advantage. However, the process for manufacturing nanowire three-dimensional multi-gate devices is rather complicated and is not compatible with the mainstream process, particularly it is difficult to use the popular MG (gate of metallic materials)/HK (gate insulating layer of high-K materials) gate stack structure, which restricts the capability of the three-dimensional multi-gate devices to improve the device performance.